1. Field of the Invention
The invention pertains generally to semiconductor devices and, more particularly, to complementary metal oxide semiconductor devices.
2. Art Background
Complementary metal oxide semiconductor (CMCS) integrated circuit devices include both n- and p-channel field effect transistors (FETs) on the same substrate. Such CMCS devices have come into increasing use because, among other advantageous properties, they consume relatively little power and exhibit relatively high noise immunity.
Despite their advantages, CMOS devices are susceptible to undesirable conduction phenomena. For example, in a typical CMOS device, depicted in FIG. 1, an n-tub (or p-tub) 40 is formed in a p- (or n-) bulk region 30. A p.sup.+ -type source 70, a p.sup.+ -type drain 80, and gate 90 constitute a p-channel FET Q1 in the n-tub 40, while an n.sup.+ -type source 110, an n.sup.+ -type drain 120, and gate 130 constitute an n-channel FET Q2 in the bulk region 30. (Voltage biases are typically applied to the substrate 20 through low resistance contacts such as the n.sup.+ -type region 60 in the n-tub 40 and the p.sup.+ -type region 100 in the p-type bulk region 30.) Inherent in the CMOS device are parasitic bipolar transistors which include a vertical p-n-p transistor T1 (shown schematically in FIG. 1) having two emitters provided by the heavily doped p.sup.+ -type regions 70 and 80, a base provided by a portion of the n-tub 40, and a collector provided by the p-type bulk region 30; and a horizontal n-p-n transistor T2 (also shown schematically in FIG. 1) having two emitters provided by the heavily doped n.sup.+ -type regions 110 and 120, a base provided by a portion of the p-type bulk region 30, and a collector provided by the n-tub 40. Under appropriate conditions, the collector current of each parasitic bipolar transistor supplies base current to the other bipolar transistor, in a positive feedback arrangement, to produce an undersirable parasitic interaction denominated latchup. (Regarding latchup see, e.g., S. M. Sze, ed., VLSI Technology, McGraw Hill, New York, 1983, p. 481). This interaction produces either a temporary malfunction of the CMOS device or, in some cases, permanent circuit damage.
A condition which must be satisfied for latchup to occur is that the product of the common emitter DC current gains of transistors T1 and T2 is greater than or equal to one. Attempts to avoid latchup have involved methods for reducing the gain of one or both transistors to achieve a product of the gains less than one.
The latchup-inducing current flowing through the base, to the collector, of a parasitic bipolar transistor is made up of minority carriers in the base. The gain of the transistor, and the possibility of latchup, is reduced by reducing this current. Such a reduction is achieved, for example, by increasing the Base Gummel Number (defined as the integral of the doping level within the base over the path length of minority carriers traversing the base) of the transistor. An increase in Base Gummel Number reduces the minority carrier base current because it decreases the base minority carrier density (in this regard see, e.g., S. M. Sze, Physics of Semiconductor Devices, Wiley, New York, 1981, 2d edition, chapter 3) and increases the likelihood of recombination between minority and majority carriers.
A method for increasing the Base Gummel Number of, for example, the horizontal parasitic bipolar transistor T2 involves increasing the spacing between the p-channel and n-channel FETs Q1 and Q2 (i.e., increasing the distance between the right side of drain region 80 and the left side of drain region 120, as viewed in FIG. 1). A sufficient increase in Base Gummel Number to significantly reduce the possibility of latchup is only achieved if the spacing between the FETs Q1 and Q2 is about 10 .mu.m (or greater). However, so great a spacing is undesirable because this results in an undesirably low device packing density, and thus wasted substrate surface area.
Yet another method for preventing latchup involves the introduction of alternate conduction paths to short-circuit those leading to undesirable, latchup-inducing interactions. For example, one such technique, depicted in FIG. 2, involves the use of a substrate 20 which includes a p-type layer 34 (in which the n-tub 40 and the FETs Q1 and Q2 are formed) epitaxially grown on a relatively heavily doped p.sup.+ -type bulk region 32. Because the p.sup.+ -type bulk region 32 constitutes a relatively low resistance path, latchup-inducing hole currents are shunted through the layer 34 into the bulk region 32, reducing interactions between the parasitic bipolar transistors T1 and T2. However, this technique is only useful provided the spacing between the p-channel and n-channel FETs Q1 and Q2 is relatively large, typically about 10 .mu.m. So large a spacing is, again, wasteful of substrate surface area.
Thus, those engaged in the development of CMOS devices have sought, thus far without success, techniques for eliminating, or substantially reducing the possibility of, latchup which avoid wasting substrate surface area, i.e., which permit relatively small spacings, less than about 10 .mu.m, between the p-channel and n-channel FETs of the device.